Field
The disclosed embodiments relate to techniques for facilitating interactions involving interrupts in computer systems. More specifically, the disclosed embodiments relate to techniques for coordinating and suppressing interrupts in network interfaces and/or computer systems.
Related Art
On busy networks, interrupting the host processor (e.g., a central-processing unit (CPU)) immediately for every received packet increases power consumption by forcing the processor to exit low-power states to handle the packet. This is especially wasteful when the packet in question turns out not to be relevant to the receiving host or turns out not to require immediate processing, as is often the case with broadcast and multicast packets. One approach to solve this has been to place some or all of the packet-processing intelligence in the network interface hardware, but this can be error prone, and requires the network interface hardware to be more capable, increasing the power requirements of that subsystem.
Another approach has been to delay interrupting the processor in the expectation that further packets will arrive, so that a batch of packets can be delivered with a single interrupt, but this also has problems. On relatively idle networks, no further packets may arrive during the delay period, with the result that after the delay expires, the interrupt still delivers only a single packet. Moreover, the enforced wait can adversely affect handling of packets that are time-sensitive. As a result, the delay may cause degradation in overall performance and user experience without yielding any beneficial energy savings. Delaying the completion of a sequence of network operations may also increase the overall energy consumption for a given task, because other system components (e.g., screen and backlighting) continue to consume full power while waiting for the artificially slowed network operations to complete.
Hence, what is needed is a mechanism for interrupting processors in computer systems without the limitations described above.